1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to semiconductor memory devices including mode registers.
2. Description of the Related Art
Semiconductor memory devices, such as dynamic random access memories (DRAMs) or static random access memories (SRAMs), typically include mode registers. Various mode setting codes are set in the mode registers to control operating characteristics of the semiconductor memory devices.
Referring to FIG. 1, an exemplary structure of conventional mode registers will be discussed. As illustrated in FIG. 1, the mode register includes code areas, such as a burst length code area 11, a burst type code area 12, a column address strobe (CAS) latency code area 13, a test mode code area 14, and a delay locked loop (DLL) reset code area 15, for controlling the operation of a semiconductor memory device. Each code area is assigned an address signal for setting mode setting codes.
In a mode register setting mode of the semiconductor memory device illustrated in FIG. 1, address signals A0 to A2 are stored in the burst length code area 11 to set a burst length, an address signal A3 is stored in the burst type code area 12 to set a burst type, address signals A4 to A6 are stored in the CAS latency code area 13 to set CAS latency, an address signal A7 is stored in the test mode code area 14 to set test operation of the semiconductor memory device, an address signal A8 is stored in the DLL resetting code area 15 to set DLL reset of the semiconductor memory device, and bank addresses BA0 and BA1 are stored in the mode register setting code area 16 to set the mode register setting mode of the semiconductor memory device.
Accordingly, conventional semiconductor memory devices support setting various mode setting codes in the mode registers having the structure illustrated in FIG. 1. However, conventional semiconductor memory devices do not typically support reading the mode setting codes that are set in the mode register. Therefore, once the mode setting codes are set in the mode registers of conventional semiconductor memory devices, the accuracy of the mode setting codes of the mode register cannot typically be checked.
For example, even when the conventional semiconductor memory device with the CAS latency code set to CAS latency 4 (CL4) in the mode register malfunctions with CAS latency 3 (CL3), the CAS latency code of the mode register cannot be checked to determine if the CAS latency code of the mode register is set to CAS latency 4 (CL4) or CAS latency 3 (CL3).
As a result, in conventional semiconductor memory devices, when malfunctions related to the mode register occur, the cause of the malfunction caused by erroneously set codes in the mode register cannot be checked. This may degrade reliability of the semiconductor memory device.